The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.
Referring now to FIG. 1, an amplifier circuit 10 without compensation is shown. A voltage source Vi delivers voltage through an impedance Z1 to an inverting input of an amplifier 16. A non-inverting input of the amplifier 16 is coupled to a reference potential such as ground. The inverting input of the amplifier 16 is coupled through a feedback impedance Z2 to an output of the amplifier 16. A load capacitance CL is coupled to the output of the amplifier 16. An output voltage VO is taken at the output of the amplifier 16. The impedances Z1 and Z2 can be resistive, capacitive and/or short circuits.
Because power supply voltage levels have been reduced to decrease the power dissipation of a host device, it has become more difficult to supply voltage to the required transistors when they are arranged in a single amplifier stage. Therefore, the amplifier 16 is sometimes implemented using two or more amplifier stages. When two or more stages are required, compensation is also typically required to increase the gain and/or bandwidth of the amplifier circuit.
Referring now to FIGS. 2A and 2B, a two stage amplifier circuit 18 with Miller compensation is shown. The amplifier 16 includes a first amplifier stage 20 having a first transconductance gm1 and a second amplifier stage 22 having a second transconductance gm2. The output of the first amplifier stage 20 is connected to an inverting input of the second amplifier stage 22. Compensation is provided by a Miller capacitor Cm having one end that is connected to the input of the second amplifier stage 22. Another end of the Miller capacitor Cm is connected to the output of the second amplifier stage 22.
The most relevant characteristics of an amplifier circuit are gain and bandwidth. The following discussion sets forth the open loop DC gain and the bandwidth of the circuit in FIG. 2B both with and without the Miller capacitance Cm. To correctly identify the bandwidth, a parasitic capacitance Cp of the second amplifier stage 22 and internal resistances R1 an R2 of the first and second amplifier stages 20 and 22 are considered as shown in FIG. 2B.
In order to derive the bandwidth, an open loop response technique is used. The open loop response technique provides information relating to the bandwidth and maximum achievable bandwidth of a circuit. The DC gain of the open loop response is determined by opening the feedback loop adjacent to the output of the second amplifier stage and attaching a voltage source to one end of the feedback loop. The output voltage is sensed at the other end of the feedback loop as shown in FIG. 2B.
To derive the bandwidth, the DC gain of the open loop response and the first dominant pole P1 are found. Assuming stable operation, there is only one pole P1 that is located below a crossover frequency. The crossover frequency is the product of the DC gain of the open loop response and the first dominant pole P1. The crossover frequency defines the bandwidth of the closed loop amplifier. The maximum available bandwidth is related to the second non-dominant pole P2.
Referring now to FIG. 3, the response of the amplifier circuit of FIG. 2B without the Miller compensation capacitor Cm is shown. The DC gain of the open loop response is
            Z      1                      Z        1            +              Z        2              ⁢      g          m      ⁢                          ⁢      1        ⁢      R    1    ⁢      g          m      ⁢                          ⁢      2        ⁢      R    2  and the circuit has a first pole at
  1            C      p        ⁢          R      1      and a second pole at
      1                  C        L            ⁢              R        2              .The first and second poles occur at frequencies that are relatively close together. The dominant pole of the first and second poles will depend upon the values of CL, CP, R1 and R2.
Referring now to FIG. 4, the response of the amplifier circuit of FIG. 2B with the Miller compensation capacitor Cm is shown. The DC gain of the open loop response is the same as the amplifier circuit without the Miller compensation capacitor Cm. The circuit has a dominant pole at
      1                  (                              C            p                    +                                    C              m                        ⁢                          A              2                                      )            ⁢              R        1              =            1                        (                                    C              p                        +                                          C                m                            ⁢                              g                                  m                  ⁢                                                                          ⁢                  2                                            ⁢                              R                2                                              )                ⁢                  R          1                      .  Multiplying the DC gain of the open loop response with P1 results in the crossover frequency of the circuit arrangement of approximately
            Z      1        ⁢          g              m        ⁢                                  ⁢        1                        (                        Z          1                +                  Z          2                    )        ⁢          C      m      since Cp<<Cmgm2R2. Further the circuit arrangement has a non-dominant pole at
                    A        2                              C          L                ⁢                  R          2                      =                                        g                          m              ⁢                                                          ⁢              2                                ⁢                      R            2                                                C            L                    ⁢                      R            2                              =                        g                      m            ⁢                                                  ⁢            2                                    C          L                      ,which relates to a barrier frequency or maximum achievable bandwidth. The dominant pole has been reduced by approximately Cmgm2R2R1. The non-dominant pole has been increased by approximately
            g              m        ⁢                                  ⁢        2                    R      2        .As a result, the dominant pole moves to a lower frequency while the non-dominant pole moves to a higher frequency.
While the Miller compensation capacitor Cm increases the bandwidth of the two stage amplifier, additional increases in bandwidth are very difficult to achieve. Increasing the bandwidth involves moving the location of the poles, which are typically in the form of
      1    RC    .The value of the parasitic capacitance Cp of the second amplifier stage cannot be reduced. The value of the resistance R1 usually cannot be reduced without adversely impacting the gain of the first amplifier stage since A1=gm1R1 and the DC gain of the open loop response.
Other performance criteria of multistage amplifiers include slew time, settling time and voltage rejection in power supply implementations. Referring now to FIGS. 5-7, slew time refers to the amount of time that is required for the output voltage to transition within a predetermined percentage of a final value after a change in the input voltage. The settling time refers to the amount of time that is required after the slew time for the output voltage to settle within a predetermined percentage of the final value. FIG. 6 shows exemplary slew and settling times.
In a power supply circuit 50 that is shown in FIG. 7, one end of a Miller compensation capacitor Cm is connected to an output of the first amplifier stage 20 and an input or gate of the second amplifier stage 22. The second amplifier stage 22 is implemented using a PMOS transistor 52 having drain that is connected to a voltage potential Vsup. The source of the transistor 52 is connected to an opposite end of the Miller capacitor Cm. A current source 54 and the load capacitor CL are connected to the source of the transistor 52 as well. The transistor 52 may be implemented using other transistor technologies.
In the circuit in FIG. 7, the slew time of the power supply circuit 50 is dependent upon the charging time of the Miller capacitance Cm. More particularly,
      slew    ⁢                  ⁢    t    =                              V          i                ⁢                  C          m                            I        i              .  The slew time is proportional to the charging time for the Miller capacitance Cm, which is not desirable.
At low frequencies, the Miller capacitance Cm is an open circuit and a feedback signal is fed back to the non-inverting input. At high frequencies, Cm shorts and a voltage divider is created between the load impedance ZL and the transconductance gm2. As a result, the output voltage
      V    o    =                              V          sup                ⁢                  Z          L                                      Z          L                +                  1                      g                          m              ⁢                                                          ⁢              2                                            .  Therefore, VO is proportional to Vsup. The power supply has relatively poor power supply voltage rejection since the fluctuations of the supply voltage Vsup are also seen in the output voltage VO.